The idea behind the capacitor is to draw current into the capacitor until the voltage is high enough to trigger the second OR gate. The delay should be some fraction of the R x C time constant (which in this case is 10,000 (Ohms) x 100 (uF) = 1 second.) I am not sure what the exact trigger voltage and therefore what the exact time it takes to trigger the second OR gate, but there is some delay now in the circuit.
I added back the loop of the first OR gate. Without this loop, the capacitor will not have enough time to charge up and the voltage would not then be high enough to trigger the second OR gate.
So, here is the new design:
... and the breadboard:
Note that the trimpot (potentiometer) might as well be a fixed 10KOhm resistor. I thought I might need to adjust the resistance value but 10KOhm seems about right.
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